Three-dimensional impedance engineering for mixed-signal system-on-chip applications

An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p - /p + Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency