A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology

A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35/spl mu/m CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data sign...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Guilar, N.J., Pak-Kim Lau, Hurst, P.J., Lewis, S.H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit topology Equalizers Equations Finite impulse response filter Intersymbol interference Parasitic capacitance Sampling methods Switches Switching circuits Transfer functions
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