A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology

A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology

A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35/spl mu/m CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data sign...

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Bibliographische Detailangaben
Hauptverfasser: Guilar, N.J., Pak-Kim Lau, Hurst, P.J., Lewis, S.H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit topology
Equalizers
Equations
Finite impulse response filter
Intersymbol interference
Parasitic capacitance
Sampling methods
Switches
Switching circuits
Transfer functions
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Beschreibung
Zusammenfassung:A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35/spl mu/m CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The equalizer is fully differential with a 4-tap transfer function. The equalizer consumes 19.5 mW at 200 MS/s and occupies an active area of 1.3mm/sup 2/.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2005.1568749