Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Exte...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Beacom, T., Buchholtz, T., Bradley, D., Randolph, J., Storino, S., Veldhuizen, M., Dance, S., Kuang, J.B., Schwinn, S., Cox, S., Ziegler, F., Kao, J., Li, C.T., Tretz, C., Cabellon, J., Freemyer, A., Tubbs, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Energy management Integrated circuit interconnections Pipelines Power control Power dissipation Signal design Silicon on insulator technology Temperature Yarn
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68/spl deg/C.
ISSN:	0886-5930 2152-3630
DOI:	10.1109/CICC.2005.1568650