Planar double gate transistors with asymmetric independent gates

Planar double gate transistors with asymmetric independent gates

Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Vari...

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Hauptverfasser: Ilicali, G., Weber, W., Rosner, W., Dreeskornfeld, L., Hartwich, J., Kretz, J., Lutz, T., Mazellier, J.-P., Stadele, M., Specht, M., Luyken, J.R., Landgraf, E., Hofmann, F., Risch, L., Kasmaier, R., Hansch, W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Capacitive sensors
Degradation
Double-gate FETs
Etching
Fabrication
Lithography
Oxidation
Silicon
Thickness control
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Beschreibung
Zusammenfassung:Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentally shown that specific off-current requirements can be fulfilled with conventional poly-Si gates.
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2005.1563562