High-density logic techniques with reduced-stack double-gate MOSFETs

High-density logic techniques with reduced-stack double-gate MOSFETs

We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), an...

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Bibliographische Detailangaben
Hauptverfasser: Meng-Hsueh Chiang, Keunwoo Kim, Ching-Te Chuang, Tretz, C.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Design engineering
Logic circuits
Logic design
Logic devices
Logic functions
Logic gates
MOSFETs
Numerical simulation
Performance analysis
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Beschreibung
Zusammenfassung:We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2005.1563544