Functional verification of pipelined processors: a case study

Functional verification of pipelined processors is one of the major bottlenecks in current system-on-chip (SOC) design methodology. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a test generation and functional coverage estimation framework for pipelined processors using Specman Elite. We have applied this methodology on a VLIW DLX architecture to demonstrate the usefulness of our approach.