A PLL based analog core tester
A novel architecture for testing the analog cores of a mixed signal system-on-chip (SoC) has been proposed. A phase locked loop (PLL) has been modified to enable an accurate analog built-in self-test (BIST) capability. The specified phase and amplitude response of the circuit-under-test (CUT) are re...
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| creator | Rashidzadeh, R. Miller, W.C. Ahmadi, M. |
| description | A novel architecture for testing the analog cores of a mixed signal system-on-chip (SoC) has been proposed. A phase locked loop (PLL) has been modified to enable an accurate analog built-in self-test (BIST) capability. The specified phase and amplitude response of the circuit-under-test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method |
| doi_str_mv | 10.1109/CCECE.2005.1557055 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1557055</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1557055</ieee_id><sourcerecordid>1557055</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-c2f871fd929bbf2d3fe193fe897e4d24bcb8f04feae747f4e2c70a5780e5ba173</originalsourceid><addsrcrecordid>eNotj81KxDAURi_-gJ3RF1CQvEDqTZr0JsshdFQo6GL2Q9LeSGV0pOnGt3fA2XxndzgfwL3CWin0TyF0oas1oq2VtYTWXkClLbWS0LSXsEJy2DjnrL6CCp1BSeT8DaxK-URE41pTweNGvPe9SLHwKOJ3PBw_xHCcWSxcFp5v4TrHQ-G7M9ew23a78CL7t-fXsOnl5HGRg86OVB699illPTaZlT-N88Rm1CYNyWU0mSOToWxYD4TRnvrYpqioWcPDv3Zi5v3PPH3F-Xd_vtX8Af0yPg0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A PLL based analog core tester</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Rashidzadeh, R. ; Miller, W.C. ; Ahmadi, M.</creator><creatorcontrib>Rashidzadeh, R. ; Miller, W.C. ; Ahmadi, M.</creatorcontrib><description>A novel architecture for testing the analog cores of a mixed signal system-on-chip (SoC) has been proposed. A phase locked loop (PLL) has been modified to enable an accurate analog built-in self-test (BIST) capability. The specified phase and amplitude response of the circuit-under-test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method</description><identifier>ISSN: 0840-7789</identifier><identifier>ISBN: 0780388852</identifier><identifier>ISBN: 9780780388857</identifier><identifier>EISSN: 2576-7046</identifier><identifier>DOI: 10.1109/CCECE.2005.1557055</identifier><language>eng</language><publisher>IEEE</publisher><subject>Built-in self-test ; Circuit faults ; Circuit testing ; Electrical fault detection ; Fault detection ; Frequency response ; Phase locked loops ; System testing ; System-on-a-chip ; Voltage control</subject><ispartof>Canadian Conference on Electrical and Computer Engineering, 2005, 2005, p.824-827</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1557055$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1557055$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rashidzadeh, R.</creatorcontrib><creatorcontrib>Miller, W.C.</creatorcontrib><creatorcontrib>Ahmadi, M.</creatorcontrib><title>A PLL based analog core tester</title><title>Canadian Conference on Electrical and Computer Engineering, 2005</title><addtitle>CCECE</addtitle><description>A novel architecture for testing the analog cores of a mixed signal system-on-chip (SoC) has been proposed. A phase locked loop (PLL) has been modified to enable an accurate analog built-in self-test (BIST) capability. The specified phase and amplitude response of the circuit-under-test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method</description><subject>Built-in self-test</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Electrical fault detection</subject><subject>Fault detection</subject><subject>Frequency response</subject><subject>Phase locked loops</subject><subject>System testing</subject><subject>System-on-a-chip</subject><subject>Voltage control</subject><issn>0840-7789</issn><issn>2576-7046</issn><isbn>0780388852</isbn><isbn>9780780388857</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81KxDAURi_-gJ3RF1CQvEDqTZr0JsshdFQo6GL2Q9LeSGV0pOnGt3fA2XxndzgfwL3CWin0TyF0oas1oq2VtYTWXkClLbWS0LSXsEJy2DjnrL6CCp1BSeT8DaxK-URE41pTweNGvPe9SLHwKOJ3PBw_xHCcWSxcFp5v4TrHQ-G7M9ew23a78CL7t-fXsOnl5HGRg86OVB699illPTaZlT-N88Rm1CYNyWU0mSOToWxYD4TRnvrYpqioWcPDv3Zi5v3PPH3F-Xd_vtX8Af0yPg0</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Rashidzadeh, R.</creator><creator>Miller, W.C.</creator><creator>Ahmadi, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A PLL based analog core tester</title><author>Rashidzadeh, R. ; Miller, W.C. ; Ahmadi, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c2f871fd929bbf2d3fe193fe897e4d24bcb8f04feae747f4e2c70a5780e5ba173</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Built-in self-test</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Electrical fault detection</topic><topic>Fault detection</topic><topic>Frequency response</topic><topic>Phase locked loops</topic><topic>System testing</topic><topic>System-on-a-chip</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Rashidzadeh, R.</creatorcontrib><creatorcontrib>Miller, W.C.</creatorcontrib><creatorcontrib>Ahmadi, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rashidzadeh, R.</au><au>Miller, W.C.</au><au>Ahmadi, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A PLL based analog core tester</atitle><btitle>Canadian Conference on Electrical and Computer Engineering, 2005</btitle><stitle>CCECE</stitle><date>2005</date><risdate>2005</risdate><spage>824</spage><epage>827</epage><pages>824-827</pages><issn>0840-7789</issn><eissn>2576-7046</eissn><isbn>0780388852</isbn><isbn>9780780388857</isbn><abstract>A novel architecture for testing the analog cores of a mixed signal system-on-chip (SoC) has been proposed. A phase locked loop (PLL) has been modified to enable an accurate analog built-in self-test (BIST) capability. The specified phase and amplitude response of the circuit-under-test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method</abstract><pub>IEEE</pub><doi>10.1109/CCECE.2005.1557055</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0840-7789 |
| ispartof | Canadian Conference on Electrical and Computer Engineering, 2005, 2005, p.824-827 |
| issn | 0840-7789 2576-7046 |
| language | eng |
| recordid | cdi_ieee_primary_1557055 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Built-in self-test Circuit faults Circuit testing Electrical fault detection Fault detection Frequency response Phase locked loops System testing System-on-a-chip Voltage control |
| title | A PLL based analog core tester |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T01%3A06%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20PLL%20based%20analog%20core%20tester&rft.btitle=Canadian%20Conference%20on%20Electrical%20and%20Computer%20Engineering,%202005&rft.au=Rashidzadeh,%20R.&rft.date=2005&rft.spage=824&rft.epage=827&rft.pages=824-827&rft.issn=0840-7789&rft.eissn=2576-7046&rft.isbn=0780388852&rft.isbn_list=9780780388857&rft_id=info:doi/10.1109/CCECE.2005.1557055&rft_dat=%3Cieee_6IE%3E1557055%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1557055&rfr_iscdi=true |