3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4times oversampling phase and frequency detector structure without a reference clock is described. The PD and FD are designed by 4times oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the TSMC 0.18mum CMOS technology and operating voltage is 1.8V