FPGA oriented design of parity sharing RS codecs

Reed Solomon codes are widely used to protect the information from errors in transmission and storage systems. RS codes rely on arithmetic in finite, or Galois fields. Most of the RS coders are based on the field GF(2/sup 8/), using a byte as a symbol and providing codewords up to 255 symbols. The drawback of this choice is the complexity of the arithmetic operation on the field GF(2/sup 8/), in particular with respect to fields with less number of elements, like GF(2/sup 4/). The use of the GF(2/sup 4/) field provides codewords up to 15 symbols. To supersede this limitation, parity sharing RS codecs has been proposed recently, even if no hardware implementation has been provided. In this paper, we analyze the hardware implementation of this kind of codes, providing a comparison with a standard RS code with the same code rate, and showing that the implementation is comparable in terms of area and there is a gain in terms of speed, in particular when the target technology is a LUT based FPGA.