Generating efficient custom FPGA soft-cores for control-dominated applications

In this paper, we present an automated flow geared toward the synthesis of application specific micro-controllers for FPGAs, targeted at control dominated applications. Our flow takes as input an application described in C, and uses profiling information to extract a specialized instruction set. This instruction set is then mapped to a generic RISC micro-architecture model, for which we generate a synthesizable VHDL description, along with its associated program. The flow has been validated on a set of representative applications and our preliminary experimental results show that our generated architectures are very competitive with FPGA vendor specific processor soft-cores, in terms of code size, resource usage and performance.