A high-speed sense-amplifier based flip-flop

A high-speed sense-amplifier based flip-flop

The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch f...

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Hauptverfasser: DeCaro, D., Napoli, E., Petra, N., Strollo, A.G.M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Flip-flops
Latches
Pipelines
Power dissipation
Propagation delay
Sampling methods
Strontium
Switches
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container_end_page II102 vol. 2
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container_start_page II/99
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container_volume 2
creator DeCaro, D.
Napoli, E.
Petra, N.
Strollo, A.G.M.
description The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25/spl mu/m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
doi_str_mv 10.1109/ECCTD.2005.1523002
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1523002</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1523002</ieee_id><sourcerecordid>1523002</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-4d8770723483905c9a5d8e784b9f628e06d1e976c3663b59f8761a3553dc92023</originalsourceid><addsrcrecordid>eNotj81qwzAQhAWlkJL6BdKLH6ByV1rrZ4_BTX8g0Et6DrK9alScVli99O1raIaBge8wwwixUdAoBfSw67rDY6MBTKOMRgB9JSpyHhYjgbW0ElUpn7AICR3qG3G_rU_p4yRLZh7rwl-FZTjnKcXEc92HstA4pSzj9J1vxXUMU-Hqkmvx_rQ7dC9y__b82m33MilnfmQ7eufAaWz9MmsGCmb07HzbU7TaM9hRMTk7oLXYG4reWRXQGBwH0qBxLe7-exMzH_OczmH-PV4-4R-dQD8X</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A high-speed sense-amplifier based flip-flop</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>DeCaro, D. ; Napoli, E. ; Petra, N. ; Strollo, A.G.M.</creator><creatorcontrib>DeCaro, D. ; Napoli, E. ; Petra, N. ; Strollo, A.G.M.</creatorcontrib><description>The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25/spl mu/m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.</description><identifier>ISBN: 9780780390669</identifier><identifier>ISBN: 0780390660</identifier><identifier>DOI: 10.1109/ECCTD.2005.1523002</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Clocks ; Flip-flops ; Latches ; Pipelines ; Power dissipation ; Propagation delay ; Sampling methods ; Strontium ; Switches</subject><ispartof>Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005, 2005, Vol.2, p.II/99-II102 vol. 2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1523002$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1523002$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>DeCaro, D.</creatorcontrib><creatorcontrib>Napoli, E.</creatorcontrib><creatorcontrib>Petra, N.</creatorcontrib><creatorcontrib>Strollo, A.G.M.</creatorcontrib><title>A high-speed sense-amplifier based flip-flop</title><title>Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005</title><addtitle>ECCTD</addtitle><description>The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25/spl mu/m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.</description><subject>Circuits</subject><subject>Clocks</subject><subject>Flip-flops</subject><subject>Latches</subject><subject>Pipelines</subject><subject>Power dissipation</subject><subject>Propagation delay</subject><subject>Sampling methods</subject><subject>Strontium</subject><subject>Switches</subject><isbn>9780780390669</isbn><isbn>0780390660</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81qwzAQhAWlkJL6BdKLH6ByV1rrZ4_BTX8g0Et6DrK9alScVli99O1raIaBge8wwwixUdAoBfSw67rDY6MBTKOMRgB9JSpyHhYjgbW0ElUpn7AICR3qG3G_rU_p4yRLZh7rwl-FZTjnKcXEc92HstA4pSzj9J1vxXUMU-Hqkmvx_rQ7dC9y__b82m33MilnfmQ7eufAaWz9MmsGCmb07HzbU7TaM9hRMTk7oLXYG4reWRXQGBwH0qBxLe7-exMzH_OczmH-PV4-4R-dQD8X</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>DeCaro, D.</creator><creator>Napoli, E.</creator><creator>Petra, N.</creator><creator>Strollo, A.G.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>A high-speed sense-amplifier based flip-flop</title><author>DeCaro, D. ; Napoli, E. ; Petra, N. ; Strollo, A.G.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-4d8770723483905c9a5d8e784b9f628e06d1e976c3663b59f8761a3553dc92023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>Flip-flops</topic><topic>Latches</topic><topic>Pipelines</topic><topic>Power dissipation</topic><topic>Propagation delay</topic><topic>Sampling methods</topic><topic>Strontium</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>DeCaro, D.</creatorcontrib><creatorcontrib>Napoli, E.</creatorcontrib><creatorcontrib>Petra, N.</creatorcontrib><creatorcontrib>Strollo, A.G.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DeCaro, D.</au><au>Napoli, E.</au><au>Petra, N.</au><au>Strollo, A.G.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A high-speed sense-amplifier based flip-flop</atitle><btitle>Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005</btitle><stitle>ECCTD</stitle><date>2005</date><risdate>2005</risdate><volume>2</volume><spage>II/99</spage><epage>II102 vol. 2</epage><pages>II/99-II102 vol. 2</pages><isbn>9780780390669</isbn><isbn>0780390660</isbn><abstract>The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25/spl mu/m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.</abstract><pub>IEEE</pub><doi>10.1109/ECCTD.2005.1523002</doi></addata></record>
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subjects Circuits
Clocks
Flip-flops
Latches
Pipelines
Power dissipation
Propagation delay
Sampling methods
Strontium
Switches
title A high-speed sense-amplifier based flip-flop
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T13%3A45%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20high-speed%20sense-amplifier%20based%20flip-flop&rft.btitle=Proceedings%20of%20the%202005%20European%20Conference%20on%20Circuit%20Theory%20and%20Design,%202005&rft.au=DeCaro,%20D.&rft.date=2005&rft.volume=2&rft.spage=II/99&rft.epage=II102%20vol.%202&rft.pages=II/99-II102%20vol.%202&rft.isbn=9780780390669&rft.isbn_list=0780390660&rft_id=info:doi/10.1109/ECCTD.2005.1523002&rft_dat=%3Cieee_6IE%3E1523002%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1523002&rfr_iscdi=true