A high-speed sense-amplifier based flip-flop

A high-speed sense-amplifier based flip-flop

The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch f...

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Hauptverfasser: DeCaro, D., Napoli, E., Petra, N., Strollo, A.G.M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Flip-flops
Latches
Pipelines
Power dissipation
Propagation delay
Sampling methods
Strontium
Switches
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Beschreibung
Zusammenfassung:The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C/sup 2/MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25/spl mu/m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
DOI:10.1109/ECCTD.2005.1523002