Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs

This paper attempts to theoretically determine the optimal number of bit-per-stage required for the CMOS low-voltage (V/sub supply/ < 2.5V/sub th/) radix-2 pipeline ADC architecture, with minimization of power dissipation and analog complexity as the overall goal. The design of a 1.5 V, 21 mW, 25 MS/s, 10-bit pipeline ADC is employed as reference. The results of the optimization analysis show that 2.5 bit-per-stage is the optimum for the 10-bit ADC design with digital error correction. This can also be generalized for any n-bit low-voltage pipeline ADC.