FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times us...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Keller, M., Kerins, T., Marnane, W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Arithmetic
Clocks
Costs
Elliptic curve cryptography
Elliptic curves
Equations
Field programmable gate arrays
Galois fields
Hamming weight
Hardware
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Beschreibung
Zusammenfassung:In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2005.1515793