A high-speed low-cost DCT architecture for HDTV applications

An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mou, Z.-J., Jutand, F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Computer architecture Discrete cosine transforms Encoding Frequency Hardware HDTV Read only memory Sampling methods
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