A high-speed low-cost DCT architecture for HDTV applications

A high-speed low-cost DCT architecture for HDTV applications

An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Mou, Z.-J., Jutand, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Computer architecture
Discrete cosine transforms
Encoding
Frequency
Hardware
HDTV
Read only memory
Sampling methods
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.< >
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.1991.150575