A high-speed low-cost DCT architecture for HDTV applications
An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computi...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1156 vol.2 |
|---|---|
| container_issue | |
| container_start_page | 1153 |
| container_title | |
| container_volume | |
| creator | Mou, Z.-J. Jutand, F. |
| description | An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.< > |
| doi_str_mv | 10.1109/ICASSP.1991.150575 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_150575</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>150575</ieee_id><sourcerecordid>150575</sourcerecordid><originalsourceid>FETCH-LOGICAL-i104t-a9c01ad997038b4c9e09e3bac1c3533f2d517ab7896800fef9fc714fbaf6b913</originalsourceid><addsrcrecordid>eNotj81KxDAUhYM_YBn7ArPKC6Te27RNL7gZOjojDChMEXdDmiY2Um1pKuLbWxjhwIGz-PgOY2uEBBHo7qnaHI8vCRJhgjnkKr9gUSoVCSR4u2QxqRKWSACQ8opFmKcgCszohsUhfCwzZDmqTEbsfsM7_96JMFrb8n74EWYIM99WNdeT6fxszfw9We6Gie-39SvX49h7o2c_fIVbdu10H2z83ytWPz7U1V4cnneL5EF4hGwWmgygbokUyLLJDFkgKxtt0MhcSpe2i4xuVElFCeCsI2cUZq7RrmgI5Yqtz1hvrT2Nk__U0-_p_Fz-AYc8SfA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A high-speed low-cost DCT architecture for HDTV applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Mou, Z.-J. ; Jutand, F.</creator><creatorcontrib>Mou, Z.-J. ; Jutand, F.</creatorcontrib><description>An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.< ></description><identifier>ISSN: 1520-6149</identifier><identifier>ISBN: 9780780300033</identifier><identifier>ISBN: 0780300033</identifier><identifier>EISSN: 2379-190X</identifier><identifier>DOI: 10.1109/ICASSP.1991.150575</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Computer architecture ; Discrete cosine transforms ; Encoding ; Frequency ; Hardware ; HDTV ; Read only memory ; Sampling methods</subject><ispartof>[Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing, 1991, p.1153-1156 vol.2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/150575$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,4036,4037,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/150575$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mou, Z.-J.</creatorcontrib><creatorcontrib>Jutand, F.</creatorcontrib><title>A high-speed low-cost DCT architecture for HDTV applications</title><title>[Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing</title><addtitle>ICASSP</addtitle><description>An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.< ></description><subject>Clocks</subject><subject>Computer architecture</subject><subject>Discrete cosine transforms</subject><subject>Encoding</subject><subject>Frequency</subject><subject>Hardware</subject><subject>HDTV</subject><subject>Read only memory</subject><subject>Sampling methods</subject><issn>1520-6149</issn><issn>2379-190X</issn><isbn>9780780300033</isbn><isbn>0780300033</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81KxDAUhYM_YBn7ArPKC6Te27RNL7gZOjojDChMEXdDmiY2Um1pKuLbWxjhwIGz-PgOY2uEBBHo7qnaHI8vCRJhgjnkKr9gUSoVCSR4u2QxqRKWSACQ8opFmKcgCszohsUhfCwzZDmqTEbsfsM7_96JMFrb8n74EWYIM99WNdeT6fxszfw9We6Gie-39SvX49h7o2c_fIVbdu10H2z83ytWPz7U1V4cnneL5EF4hGwWmgygbokUyLLJDFkgKxtt0MhcSpe2i4xuVElFCeCsI2cUZq7RrmgI5Yqtz1hvrT2Nk__U0-_p_Fz-AYc8SfA</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Mou, Z.-J.</creator><creator>Jutand, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>A high-speed low-cost DCT architecture for HDTV applications</title><author>Mou, Z.-J. ; Jutand, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-a9c01ad997038b4c9e09e3bac1c3533f2d517ab7896800fef9fc714fbaf6b913</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Clocks</topic><topic>Computer architecture</topic><topic>Discrete cosine transforms</topic><topic>Encoding</topic><topic>Frequency</topic><topic>Hardware</topic><topic>HDTV</topic><topic>Read only memory</topic><topic>Sampling methods</topic><toplevel>online_resources</toplevel><creatorcontrib>Mou, Z.-J.</creatorcontrib><creatorcontrib>Jutand, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mou, Z.-J.</au><au>Jutand, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A high-speed low-cost DCT architecture for HDTV applications</atitle><btitle>[Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing</btitle><stitle>ICASSP</stitle><date>1991</date><risdate>1991</risdate><spage>1153</spage><epage>1156 vol.2</epage><pages>1153-1156 vol.2</pages><issn>1520-6149</issn><eissn>2379-190X</eissn><isbn>9780780300033</isbn><isbn>0780300033</isbn><abstract>An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.< ></abstract><pub>IEEE</pub><doi>10.1109/ICASSP.1991.150575</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1520-6149 |
| ispartof | [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing, 1991, p.1153-1156 vol.2 |
| issn | 1520-6149 2379-190X |
| language | eng |
| recordid | cdi_ieee_primary_150575 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Computer architecture Discrete cosine transforms Encoding Frequency Hardware HDTV Read only memory Sampling methods |
| title | A high-speed low-cost DCT architecture for HDTV applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T13%3A46%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20high-speed%20low-cost%20DCT%20architecture%20for%20HDTV%20applications&rft.btitle=%5BProceedings%5D%20ICASSP%2091:%201991%20International%20Conference%20on%20Acoustics,%20Speech,%20and%20Signal%20Processing&rft.au=Mou,%20Z.-J.&rft.date=1991&rft.spage=1153&rft.epage=1156%20vol.2&rft.pages=1153-1156%20vol.2&rft.issn=1520-6149&rft.eissn=2379-190X&rft.isbn=9780780300033&rft.isbn_list=0780300033&rft_id=info:doi/10.1109/ICASSP.1991.150575&rft_dat=%3Cieee_6IE%3E150575%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=150575&rfr_iscdi=true |