Return path assumption validation for inductance modeling in digital design

Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	David, L., Cregut, C., Huret, F., Quere, Y., Nyer, F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit noise Circuit simulation Delay effects Delay estimation Digital circuits Frequency Inductance Integrated circuit interconnections RLC circuits Working environment noise
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