Return path assumption validation for inductance modeling in digital design

Return path assumption validation for inductance modeling in digital design

Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematic...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: David, L., Cregut, C., Huret, F., Quere, Y., Nyer, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit noise
Circuit simulation
Delay effects
Delay estimation
Digital circuits
Frequency
Inductance
Integrated circuit interconnections
RLC circuits
Working environment noise
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Beschreibung
Zusammenfassung:Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing pre-layout effective inductance estimations are suggested.
DOI:10.1109/SPI.2005.1500909