Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while main...

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Hauptverfasser: Mincheol Park, Jung-Dal Choi, Sung-Hoi Hur, Jong-Ho Park, Joon-Hee Lee, Jin-Taek Park, Jong-Sun Sel, Jong-Won Kim, Sang-Bin Song, Jung-Young Lee, Ji-Hwon Lee, Suk-Joon Son, Yong-Seok Kim, Soo-Jin Chai, Kyeong-Tae Kim, Kinam Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Dielectric constant
Dielectric materials
Dielectric measurements
Doping
Flash memory
Interference
Nonvolatile memory
Silicon
Space technology
Voltage
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Beschreibung
Zusammenfassung:We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2005.1497073