Two-chip implemented, wafer-level hermetic packaged accelerometer for tactical and inertial applications

A two chip implemented, wafer-level hermetically packaged accelerometer is presented. The accelerometer core is fabricated using the SBM (sacrificial bulk micromachining) process. The fabricated accelerometer core accomplishes high performance, high yield and high reliability by the inherent high-aspect-ratio, footing-free advantages of the SBM process. In order to protect the accelerometer core from environmental changes, a wafer-level hermetic packaging process is performed by using glass-silicon anodic bonding. The capacitive detection circuit adopts an EEPROM trimmable architecture to reduce the die-to-die variations. The fabricated accelerometer has the noise equivalent acceleration resolution of 43 /spl mu/g, input range of /spl plusmn/10 g, Output nonlinearity of 0.1% FSO, scale factor of 130 mV/g, and 4-hr bias stability of 1.10 mg.