Low-power small-area digital I/O cell
A novel low-power and small-area digital I/O cell is proposed in this work. The new input/output (I/O) cell drastically reduces the I/O power consumption, which has been considered as the major power dissipation of the whole chip. The maximum operating clock is 500 MHz given a 10-pF offchip load. On...
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Veröffentlicht in: | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2005-08, Vol.52 (8), p.508-511 |
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