Low-power small-area digital I/O cell

A novel low-power and small-area digital I/O cell is proposed in this work. The new input/output (I/O) cell drastically reduces the I/O power consumption, which has been considered as the major power dissipation of the whole chip. The maximum operating clock is 500 MHz given a 10-pF offchip load. On top of the power saving feature, the proposed cell occupies merely 10535.2=4167.45 (transmitter)+6367.8 (receiver) /spl mu/m/sup 2/ which is far less than any prior commercially available I/O and low-voltage differential signaling I/O cells. Physical measurements of the proposed I/O cells show that the delays of the transmitter and the receiver are 1.1 and 1.8 ns, respectively. The largest power/bandwidth of the proposed design is 38.9 /spl mu/W/MHz when transmitting.