A sub-10ps multi-phase sampling system using redundancy
The feasibility of sampling with clock phases spaced by a bin size of
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| creator | Li-min Lee Chih-Kong Ken Yang |
| description | The feasibility of sampling with clock phases spaced by a bin size of |
| doi_str_mv | 10.1109/ISSCC.2005.1494093 |
| format | Conference Proceeding |
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The phase spacing is limited only by uncorrelated thermal noise in the system. Redundancy is introduced in addition to interpolators and offset compensation to reduce static errors to 1.5ps.</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 0780389042</identifier><identifier>ISBN: 9780780389045</identifier><identifier>EISSN: 2376-8606</identifier><identifier>DOI: 10.1109/ISSCC.2005.1494093</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Clocks ; Jitter ; Noise reduction ; Phase measurement ; Phase noise ; Redundancy ; Sampling methods ; System testing ; Voltage</subject><ispartof>ISSCC. 2005 IEEE International Digest of Technical Papers. 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Redundancy is introduced in addition to interpolators and offset compensation to reduce static errors to 1.5ps.</description><subject>Circuits</subject><subject>Clocks</subject><subject>Jitter</subject><subject>Noise reduction</subject><subject>Phase measurement</subject><subject>Phase noise</subject><subject>Redundancy</subject><subject>Sampling methods</subject><subject>System testing</subject><subject>Voltage</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>0780389042</isbn><isbn>9780780389045</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tOwzAURC0eEqH0B2CTH3C49o0fd1lFUCpVYtHuKzt2ISiJojhZ5O8porMZnc3oDGPPAgohgF53h0NVFRJAFaKkEghvWCbRaG416Fv2CMYCWoJS3rEMBCHXCuGBrVP6gUusNBYhY2aTp9lzAUPKu7mdGj58uxTz5LqhbfqvPC1pil0-pz8YY5j74Pp6eWL3Z9emuL72ih3f347VB99_bnfVZs8bgok7j6TAaOc9BvSahAoRSqNckLVS2iISwUUEvNVGIGof69KcawjBePK4Yi__s02M8TSMTefG5XS9jL985kdk</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Li-min Lee</creator><creator>Chih-Kong Ken Yang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A sub-10ps multi-phase sampling system using redundancy</title><author>Li-min Lee ; Chih-Kong Ken Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-ab395076abb3d3b6915de0475ad2c5568339908300b8671336bec47fc0dd7b9b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>Jitter</topic><topic>Noise reduction</topic><topic>Phase measurement</topic><topic>Phase noise</topic><topic>Redundancy</topic><topic>Sampling methods</topic><topic>System testing</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Li-min Lee</creatorcontrib><creatorcontrib>Chih-Kong Ken Yang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li-min Lee</au><au>Chih-Kong Ken Yang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A sub-10ps multi-phase sampling system using redundancy</atitle><btitle>ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005</btitle><stitle>ISSCC</stitle><date>2005</date><risdate>2005</risdate><spage>510</spage><epage>613 Vol. 1</epage><pages>510-613 Vol. 1</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>0780389042</isbn><isbn>9780780389045</isbn><abstract>The feasibility of sampling with clock phases spaced by a bin size of <10ps for a multi-channel system in a 0.18 /spl mu/m CMOS technology is demonstrated. The phase spacing is limited only by uncorrelated thermal noise in the system. Redundancy is introduced in addition to interpolators and offset compensation to reduce static errors to 1.5ps.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2005.1494093</doi></addata></record> |
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| ispartof | ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.510-613 Vol. 1 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_1494093 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Clocks Jitter Noise reduction Phase measurement Phase noise Redundancy Sampling methods System testing Voltage |
| title | A sub-10ps multi-phase sampling system using redundancy |
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