A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 20GB/s 1.8V 256MB DRAM is designed and fabricated using an 80nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with a cascaded pre-emphasis transmitter to achieve a 10Gbit/s/pin data rate.

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Bibliographische Detailangaben
Hauptverfasser: Kyu-Hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Dong-Jin Lee, Gyung-Su Byun, Hoon Lee, Jae-Hyoung Lee, Jung Sunwoo, Jung-Hwan Choi, Jun-Wan Chai, Changhyun Kim, Soo-In Cho
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Frequency conversion
Inverters
Jitter
Noise reduction
Phase locked loops
Random access memory
Ring oscillators
Transmitters
Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:A 20GB/s 1.8V 256MB DRAM is designed and fabricated using an 80nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with a cascaded pre-emphasis transmitter to achieve a 10Gbit/s/pin data rate.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1494073