A 0.12 /spl mu/m CMOS DVB-T tuner

A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration...

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Hauptverfasser: Saias, D., Montaudon, F., Andre, E., Bailleul, F., Bely, M., Busson, P., Dedieu, S., Dezzani, A., Moutard, A., Provins, G., Rouat, E., Roux, J., Wagner, G., Paillardet, F.
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creator Saias, D.
Montaudon, F.
Andre, E.
Bailleul, F.
Bely, M.
Busson, P.
Dedieu, S.
Dezzani, A.
Moutard, A.
Provins, G.
Rouat, E.
Roux, J.
Wagner, G.
Paillardet, F.
description A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.
doi_str_mv 10.1109/ISSCC.2005.1494053
format Conference Proceeding
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ispartof ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.430-431 Vol. 1
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects CMOS process
Digital video broadcasting
Filters
Gain measurement
Impedance matching
Linearity
Noise measurement
Phase noise
Tuners
Voltage-controlled oscillators
title A 0.12 /spl mu/m CMOS DVB-T tuner
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