A 0.12 /spl mu/m CMOS DVB-T tuner

A 0.12 /spl mu/m CMOS DVB-T tuner

A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration...

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Bibliographische Detailangaben
Hauptverfasser: Saias, D., Montaudon, F., Andre, E., Bailleul, F., Bely, M., Busson, P., Dedieu, S., Dezzani, A., Moutard, A., Provins, G., Rouat, E., Roux, J., Wagner, G., Paillardet, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
Digital video broadcasting
Filters
Gain measurement
Impedance matching
Linearity
Noise measurement
Phase noise
Tuners
Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1494053