A self-biased PLL with current-mode filter for clock generation

A self-biased PLL with current-mode filter for clock generation

A self-biased PLL with current mode filter is designed to achieve a bandwidth that scales with reference clock and is independent of PVT and multiplication factor. It provides wide tuning range with a simple robust structure. The 0.2mm/sup 2/ chip is fabricated in 0.35 /spl mu/m CMOS. Running at 800...

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Bibliographische Detailangaben
Hauptverfasser: Gang Yan, Chenxiao Ren, Zhendong Guo, Qing Ouyang, Zhongyuan Chang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
1f noise
Bandwidth
Charge pumps
Clocks
Filters
Frequency
Jitter
Phase locked loops
Temperature
Transconductance
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Beschreibung
Zusammenfassung:A self-biased PLL with current mode filter is designed to achieve a bandwidth that scales with reference clock and is independent of PVT and multiplication factor. It provides wide tuning range with a simple robust structure. The 0.2mm/sup 2/ chip is fabricated in 0.35 /spl mu/m CMOS. Running at 800MHz, the phase jitter is 72.7ps/sub pp/ and the power consumption is 20mW.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1494048