A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

An 8b 200MS/s 2.8b-per-stage pipelined ADC is realized in a 0.18/spl mu/m CMOS process. By using partially switched operational amplifiers, the ADC consumes 30mW from a 1.8V supply and occupies 0.15mm/sup 2/. The ADC achieves 47.3dB SNDR, 55.8dB SFDR, and 7.6 ENOB for a 90MHz input at 200MS/s.

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Bibliographische Detailangaben
Hauptverfasser: Hwi-Cheol Kim, Deog-Kyoon Jeong, Wonchan Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Capacitors
CMOS technology
Communication switching
Energy consumption
Mixed analog digital integrated circuits
Pipelines
Sampling methods
Switches
Voltage
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Beschreibung
Zusammenfassung:An 8b 200MS/s 2.8b-per-stage pipelined ADC is realized in a 0.18/spl mu/m CMOS process. By using partially switched operational amplifiers, the ADC consumes 30mW from a 1.8V supply and occupies 0.15mm/sup 2/. The ADC achieves 47.3dB SNDR, 55.8dB SFDR, and 7.6 ENOB for a 90MHz input at 200MS/s.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493980