A 1V 24GHz 17.5mW PLL in 0.18/spl mu/m CMOS

A 1V 24GHz fully integrated PLL is designed in a 0.18/spl mu/m. CMOS process using a transformer-feedback VCO and a stacked frequency divider. The PLL measures an in-band phase noise of -106.3dBc/Hz at 100kHz offset and an out-of-band phase noise of -119.1dBc/Hz at 10MHz offset. It consumes 17.5mW f...

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Hauptverfasser: Ng, A.W.L., Leung, G.C.T., Kwok, K.-C., Leung, L.L.K., Luong, H.C.
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:A 1V 24GHz fully integrated PLL is designed in a 0.18/spl mu/m. CMOS process using a transformer-feedback VCO and a stacked frequency divider. The PLL measures an in-band phase noise of -106.3dBc/Hz at 100kHz offset and an out-of-band phase noise of -119.1dBc/Hz at 10MHz offset. It consumes 17.5mW from a 1V supply and occupying an area of 0.55mm/sup 2/.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493917