A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications

A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications

An H.264/AVC encoder is implemented on a 31.72mm/sup 2/ die with 0.18/spl mu/m CMOS technology. A four-stage macroblock pipelined architecture encodes 720p 30f/s HDTV videos in real time at 108MHz. The encoded video quality is competitive with reference software requiring 3.6TOPS on a general-purpos...

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Hauptverfasser: Yu-Wen Huang, Tung-Chien Chen, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Chi-Shi Chen, Chun-Fu Shen, Shyh-Yih Ma, Tu-Chih Wang, Bing-Yu Hsieh, Hung-Chi Fang, Liang-Gee Chen
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Automatic voltage control
Bandwidth
Bit rate
CMOS technology
Digital video broadcasting
HDTV
Heat engines
Motion estimation
Pipeline processing
Throughput
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Beschreibung
Zusammenfassung:An H.264/AVC encoder is implemented on a 31.72mm/sup 2/ die with 0.18/spl mu/m CMOS technology. A four-stage macroblock pipelined architecture encodes 720p 30f/s HDTV videos in real time at 108MHz. The encoded video quality is competitive with reference software requiring 3.6TOPS on a general-purpose processor-based platform.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493902