Junction leakage induced by silicon dislocation in a 0.13 micron logic process

Generally, static-random access memory (SRAM) is used to debug the logic process as a technology qualification vehicle (TQV). As a 0.13 micron logic process was developed, some dies suffered gross function failure, the major yield-limiting defect. The paper presents silicon dislocation across the LDD (lightly-doped drain) area, causing p-n junction leakage. Mosaid engineering tester and passive voltage contrast (PVC) were used to locate the failure sites; focus ion beam (FIB), transmission electronic microscope (TEM) and junction stain were used to identify the root cause. In addition, the failure mechanisms are discussed.