An ESD protected RFIC power amplifier design

This paper presents the development of electrostatic discharge (ESD) protection circuitry for a three-stage power amplifier (PA) designed for 1.9 GHz digitally enhanced cordless telephone (DECT) applications. Through careful RF and ESD circuit co-design, good RF performance and ESD immunity are achieved. The PA features a high gain of 26 dB at an output power of 25 dBm, which remained unaffected due to the inclusion of ESD circuitry. The circuit's power added efficiency (PAE) is also relatively unaffected, remaining at around 43%. The circuit is fabricated using a commercial 0.5 /spl mu/m SiGe-HBT process. The design is capable of protecting the PA from -4 kV to +1.5 kV human body model (HBM) ESD stresses.