A fully integrated receiver front-end reconfigured by PLL

A fully integrated receiver front-end, reconfigured by a frequency locking scheme using a PLL, is implemented in a 0.18 /spl mu/m triple-well CMOS technology. The receiver front-end is composed of a discretely tunable low noise amplifier (DT-LNA), a quadrature down mixer, and a discretely and continuously tunable frequency synthesizer (DCT-FS) with an integrated DCT-VCO. The front-end measured performances are 2-2.75 GHz tuning range by about 50 MHz steps, 40 dB voltage gain, -25 dBm IIP3, 2.1-2.7 dB DSB NF. The synthesizer features a phase noise of -80 dBc/Hz at in-band and -120 dBc/Hz at 1 MHz offset. The receiver front-end consumes 30 mA from a 1.8 V supply.