A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5...

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Bibliographische Detailangaben

Hauptverfasser:	Varzaghani, A., Yang, C.-K.K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analog-digital conversion Clocks CMOS technology Decision feedback equalizers Delay Intersymbol interference Pipeline processing Semiconductor device measurement Signal resolution Signal to noise ratio
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