A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8/spl times/1.6mm/sup 2/ chip is fabricated in 0.18/spl mu/m CMOS technology and consumes 780mW at 1.8V power-supply.