A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE
A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5...
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| creator | Varzaghani, A. Yang, C.-K.K. |
| description | A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8/spl times/1.6mm/sup 2/ chip is fabricated in 0.18/spl mu/m CMOS technology and consumes 780mW at 1.8V power-supply. |
| doi_str_mv | 10.1109/VLSIC.2005.1469396 |
| format | Conference Proceeding |
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Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8/spl times/1.6mm/sup 2/ chip is fabricated in 0.18/spl mu/m CMOS technology and consumes 780mW at 1.8V power-supply.</description><subject>Analog-digital conversion</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Decision feedback equalizers</subject><subject>Delay</subject><subject>Intersymbol interference</subject><subject>Pipeline processing</subject><subject>Semiconductor device measurement</subject><subject>Signal resolution</subject><subject>Signal to noise ratio</subject><issn>2158-5601</issn><issn>2158-5636</issn><isbn>490078401X</isbn><isbn>9784900784017</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9z81Kw0AYheHBH7Ct3oBu5gKc9PvmN7MsMa2FgIuquCuTzKSOpI0kg-LdW7C4OosHDryE3CJkiGDnr9VmXWQcQGUotRVWn5EJR5UzpYU-J1NpAUwuAd8u_gHwikzH8QOAK-RqQsoF1avNfLynktUx0SE0IX6FgbqD6_odSz3zcReT62jTH46QjvYd0zsN-zp4Hzx9WJbX5LJ13RhuTjsjL8vyuXhk1dNqXSwqFtGoxKxpjW64qZ1otLAQELWARqG3mEtpeAveylwKabXgRks00CJ3CiTPdcjFjNz9_cYQwvZziHs3_GxP-eIXnoxJFg</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Varzaghani, A.</creator><creator>Yang, C.-K.K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE</title><author>Varzaghani, A. ; Yang, C.-K.K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-97f76c27ba3c6390e11630c51d9184472f0d9484349632764170f12a504286e83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Analog-digital conversion</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Decision feedback equalizers</topic><topic>Delay</topic><topic>Intersymbol interference</topic><topic>Pipeline processing</topic><topic>Semiconductor device measurement</topic><topic>Signal resolution</topic><topic>Signal to noise ratio</topic><toplevel>online_resources</toplevel><creatorcontrib>Varzaghani, A.</creatorcontrib><creatorcontrib>Yang, C.-K.K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Varzaghani, A.</au><au>Yang, C.-K.K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE</atitle><btitle>Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005</btitle><stitle>VLSIC</stitle><date>2005</date><risdate>2005</risdate><spage>322</spage><epage>325</epage><pages>322-325</pages><issn>2158-5601</issn><eissn>2158-5636</eissn><isbn>490078401X</isbn><isbn>9784900784017</isbn><abstract>A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8/spl times/1.6mm/sup 2/ chip is fabricated in 0.18/spl mu/m CMOS technology and consumes 780mW at 1.8V power-supply.</abstract><pub>IEEE</pub><doi>10.1109/VLSIC.2005.1469396</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 2158-5601 |
| ispartof | Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.322-325 |
| issn | 2158-5601 2158-5636 |
| language | eng |
| recordid | cdi_ieee_primary_1469396 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog-digital conversion Clocks CMOS technology Decision feedback equalizers Delay Intersymbol interference Pipeline processing Semiconductor device measurement Signal resolution Signal to noise ratio |
| title | A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE |
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