A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps /spl times/ 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write with...

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Hauptverfasser: Jung-Hwan Choi, Young-Soo Sohn, Chan-Kyoung Kim, Won-Ki Park, Jae-Hyung Lee, Uksong Kang, Gyung-Su Byun, In-Soo Park, Byung-Chul Kim, Hong-Sun Hwang, Chang-Hyun Kim, Soo-In Cho
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuits
Clocks
Delay
Energy consumption
Frequency
Inverters
MOS devices
Phase locked loops
Random access memory
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Beschreibung
Zusammenfassung:A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps /spl times/ 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write without 10 pre-charge scheme was employed. The power consumption and area of the chip are 2.4W and 7.2/spl times/10.2mm/sup 2/ respectively.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2005.1469331