A clock recovery circuit using half-rate 4/spl times/-oversampling PD

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input...

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Hauptverfasser:	Hyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge pumps Circuits Clocks CMOS technology Optical signal processing Phase detection Phase frequency detector Sampling methods Signal design Voltage-controlled oscillators
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creator	Hyung-Wook Jang Sung-Sop Lee Jin-Ku Kang
description	In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 /spl mu/m CMOS technology and operating voltage is 2.5V. The circuit operates between 480 Mbit/s-1.5 Gbit/s.
doi_str_mv	10.1109/ISCAS.2005.1465056
format	Conference Proceeding
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The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 /spl mu/m CMOS technology and operating voltage is 2.5V. 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The circuit operates between 480 Mbit/s-1.5 Gbit/s.</description><subject>Charge pumps</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Optical signal processing</subject><subject>Phase detection</subject><subject>Phase frequency detector</subject><subject>Sampling methods</subject><subject>Signal design</subject><subject>Voltage-controlled oscillators</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9780780388345</isbn><isbn>0780388348</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssKwjAURC8-wKL9Ad3kB9LevNq6FB_oTtC9hBA1mmpJquDfq-DaYWAW5ywGYMwwYwyn-WY3n-0yjqgyJguFquhAwpmqKFNcdSGdlhV-KqpKSNWDBHnJqBTIB5DGeMFPpBIlLxJYzojxd3MlwZr704YXMS6Yh2vJI7rbiZy1P9KgW0tkHhtPWlfbmNOvGnXd-K-zXYygf9Q-2vS3Q5islvv5mjpr7aEJrtbhdfidFf_pG66CPoI</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Hyung-Wook Jang</creator><creator>Sung-Sop Lee</creator><creator>Jin-Ku Kang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A clock recovery circuit using half-rate 4/spl times/-oversampling PD</title><author>Hyung-Wook Jang ; Sung-Sop Lee ; Jin-Ku Kang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_14650563</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Charge pumps</topic><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Optical signal processing</topic><topic>Phase detection</topic><topic>Phase frequency detector</topic><topic>Sampling methods</topic><topic>Signal design</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Hyung-Wook Jang</creatorcontrib><creatorcontrib>Sung-Sop Lee</creatorcontrib><creatorcontrib>Jin-Ku Kang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hyung-Wook Jang</au><au>Sung-Sop Lee</au><au>Jin-Ku Kang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A clock recovery circuit using half-rate 4/spl times/-oversampling PD</atitle><btitle>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2005</date><risdate>2005</risdate><spage>2192</spage><epage>2195 Vol. 3</epage><pages>2192-2195 Vol. 3</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9780780388345</isbn><isbn>0780388348</isbn><abstract>In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 /spl mu/m CMOS technology and operating voltage is 2.5V. The circuit operates between 480 Mbit/s-1.5 Gbit/s.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2005.1465056</doi></addata></record>
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subjects	Charge pumps Circuits Clocks CMOS technology Optical signal processing Phase detection Phase frequency detector Sampling methods Signal design Voltage-controlled oscillators
title	A clock recovery circuit using half-rate 4/spl times/-oversampling PD
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