A clock recovery circuit using half-rate 4/spl times/-oversampling PD

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 /spl mu/m CMOS technology and operating voltage is 2.5V. The circuit operates between 480 Mbit/s-1.5 Gbit/s.