Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADC. The paper continues by analyzing the optimal design for low power of the scaled back-end stages. Finally, a model is proposed to estimate the power per stage, and hence total power consumption of the pipeline ADC.