ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective ex...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mergens, M., Wybo, G., Van Camp, B., Keppens, B., De Ranter, F., Verhaege, K., Jozwiak, P., Armer, J., Russ, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific processors Circuit synthesis Clamps CMOS technology Diodes Electrostatic discharge Protection Radio frequency Thyristors Voltage
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