ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective ex...

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Hauptverfasser: Mergens, M., Wybo, G., Van Camp, B., Keppens, B., De Ranter, F., Verhaege, K., Jozwiak, P., Armer, J., Russ, C.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application specific processors
Circuit synthesis
Clamps
CMOS technology
Diodes
Electrostatic discharge
Protection
Radio frequency
Thyristors
Voltage
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Beschreibung
Zusammenfassung:This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2005.1464807