Checkers for SystemC designs

Today's complex systems are modeled on a high level of abstraction. In this context, C/C++-based description languages, like SystemC, become very important. The modeling features of SystemC enable adequate levels of abstraction, hardware/software integration and fast executable specifications. Using the SystemC design methodology, a system is partitioned into hardware and software. Then the modules are refined down to the implementation. Besides efficient modeling, the correct functional behavior is very important. Already today up to 80% of the overall design costs are due to verification. As the complete system cannot be formally verified, checking of the functional behavior during operation has to be considered. In this paper an approach is presented that allows to check temporal properties for a SystemC design not only during simulation, but also after fabrication inform of an on-line test. The method translates the properties into synthesizable SystemC instructions. By this, the properties can be checked like HDL assertions during simulation and after production since they can be synthesized together with the system. The proposed approach enables a concise circuit and system verification methodology.