An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resol...

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Hauptverfasser: Foley, R.F., Kavanagh, R.C., Marnane, W.P., Egan, M.G.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Counting circuits
Delay
Digital modulation
Field programmable gate arrays
Frequency
Power generation
Pulse modulation
Pulse width modulation
Pulsed power supplies
Space vector pulse width modulation
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Beschreibung
Zusammenfassung:This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.
ISSN:1048-2334
2470-6647
DOI:10.1109/APEC.2005.1453214