Fully-depleted SOI devices with elevated source/drain structure
0.35/spl mu/m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure were fabricated by novel technology. Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthre...
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creator | Jun Lian Chaohe Hai |
description | 0.35/spl mu/m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure were fabricated by novel technology. Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthreshold slope of PMOSFETs is 69mv/decade. The saturation current of NMOSFETs and PMOSFETs is 375/spl mu/A/um and 170/spl mu/A/um either. The saturation current of 1.2/spl mu/ NMOSFETs was increased by 32% with elevated source/drain structure. The saturation current of 1.2/spl mu/m PMOSFETs was increased by 24%. The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 75ps with 3 V supply voltage. |
doi_str_mv | 10.1109/ICSICT.2004.1435008 |
format | Conference Proceeding |
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Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthreshold slope of PMOSFETs is 69mv/decade. The saturation current of NMOSFETs and PMOSFETs is 375/spl mu/A/um and 170/spl mu/A/um either. The saturation current of 1.2/spl mu/ NMOSFETs was increased by 32% with elevated source/drain structure. The saturation current of 1.2/spl mu/m PMOSFETs was increased by 24%. The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 75ps with 3 V supply voltage.</description><identifier>ISBN: 078038511X</identifier><identifier>ISBN: 9780780385115</identifier><identifier>DOI: 10.1109/ICSICT.2004.1435008</identifier><language>eng</language><publisher>IEEE</publisher><subject>Amorphous silicon ; Etching ; Implants ; MOSFETs ; Silicides ; Space technology ; Temperature ; Thin film devices ; Tiles ; Tin</subject><ispartof>Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004, 2004, Vol.1, p.287-290 vol.1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1435008$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1435008$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jun Lian</creatorcontrib><creatorcontrib>Chaohe Hai</creatorcontrib><title>Fully-depleted SOI devices with elevated source/drain structure</title><title>Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004</title><addtitle>ICSICT</addtitle><description>0.35/spl mu/m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure were fabricated by novel technology. Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthreshold slope of PMOSFETs is 69mv/decade. The saturation current of NMOSFETs and PMOSFETs is 375/spl mu/A/um and 170/spl mu/A/um either. The saturation current of 1.2/spl mu/ NMOSFETs was increased by 32% with elevated source/drain structure. The saturation current of 1.2/spl mu/m PMOSFETs was increased by 24%. The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 75ps with 3 V supply voltage.</description><subject>Amorphous silicon</subject><subject>Etching</subject><subject>Implants</subject><subject>MOSFETs</subject><subject>Silicides</subject><subject>Space technology</subject><subject>Temperature</subject><subject>Thin film devices</subject><subject>Tiles</subject><subject>Tin</subject><isbn>078038511X</isbn><isbn>9780780385115</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81KAzEUhQMiVGufoJt5gZnem0z-ViKD1YFCF63QXYmTOxiJWpKZSt_eSns2Z_FxPjiMzREqRLCLttm0zbbiAHWFtZAA5obdgzYgjETcTdgs5084R1glLb9jj8sxxlPp6RBpIF9s1m3h6Rg6ysVvGD4KinR0_yT_jKmjhU8ufBd5SGM3jIke2G3vYqbZtafsbfm8bV7L1fqlbZ5WZUCQQymV1VpZqToJlogQVS05GpQogDvSVr07bTrRqxp77jl6MBpq2YP1BriYsvnFG87r_SGFL5dO--tH8QfP4UZe</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Jun Lian</creator><creator>Chaohe Hai</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2004</creationdate><title>Fully-depleted SOI devices with elevated source/drain structure</title><author>Jun Lian ; Chaohe Hai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-569776956c509eee11645218151302ae796ba78c3f641f2d21d087045f09d8023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Amorphous silicon</topic><topic>Etching</topic><topic>Implants</topic><topic>MOSFETs</topic><topic>Silicides</topic><topic>Space technology</topic><topic>Temperature</topic><topic>Thin film devices</topic><topic>Tiles</topic><topic>Tin</topic><toplevel>online_resources</toplevel><creatorcontrib>Jun Lian</creatorcontrib><creatorcontrib>Chaohe Hai</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jun Lian</au><au>Chaohe Hai</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Fully-depleted SOI devices with elevated source/drain structure</atitle><btitle>Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004</btitle><stitle>ICSICT</stitle><date>2004</date><risdate>2004</risdate><volume>1</volume><spage>287</spage><epage>290 vol.1</epage><pages>287-290 vol.1</pages><isbn>078038511X</isbn><isbn>9780780385115</isbn><abstract>0.35/spl mu/m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure were fabricated by novel technology. Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthreshold slope of PMOSFETs is 69mv/decade. The saturation current of NMOSFETs and PMOSFETs is 375/spl mu/A/um and 170/spl mu/A/um either. The saturation current of 1.2/spl mu/ NMOSFETs was increased by 32% with elevated source/drain structure. The saturation current of 1.2/spl mu/m PMOSFETs was increased by 24%. The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 75ps with 3 V supply voltage.</abstract><pub>IEEE</pub><doi>10.1109/ICSICT.2004.1435008</doi></addata></record> |
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subjects | Amorphous silicon Etching Implants MOSFETs Silicides Space technology Temperature Thin film devices Tiles Tin |
title | Fully-depleted SOI devices with elevated source/drain structure |
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