High performance 27 nm gate length CMOS device with EOT 1.4 nm gate oxynitride and strained technology

Scaling CMOS device towards deep sub-30nm gate length generation requires innovations in a device design and technologies for improving short channel effect (SCE) control and drive current / off state current (I/sub on/ / I/sub off/) ratio. In this paper high performance 27 nm gate length CMOS devices and 36 nm gate length 32 CMOS frequency dividers are demonstrated successfully. The offset S/D extension structure, Ge pre-amorphization implantation (PAI) combining low energy implantation (LEI) for ultra-shallow S/D extension induce a large uniaxial compressive strain in the channel region, 1.4 nm EOT gate oxynitride by oxidation of nitrogen-implanted silicon substrate, super steep retrograde channel doping with heavy ion implantation, 20 nm poly-Si gate patterning with high selectivity, high anisotropy and accuracy; and Co/Ti dual refractory metal SALICIDE feature the device. By these innovations, very good SCE control and I/sub on//I/sub off/ ratio are achieved. At power supply voltage V/sub DD/ of 1.5V, 27 nm gate length CMOS device with drive current I/sub on/ of 850 A/m for NMOS and 506 A/m for PMOS are achieved at off-state leakage W of 7.3 nA/m for NMOS and 4.2 nA/m for PMOS.