A low-power 16-bit 500 kS/s ADC

A low-power 16-bit 500 kS/s ADC

A 6.2 mW 16-bit 500 kSps charge redistribution self calibrating successive approximation analog-to-digital converter (ADC) is described. It has an input range of 2 V, a resolution of 16 bits and operates with +/- 1.5 V supplies. Simulations show a signal-to-noise ratio of 95 dB for an effective accu...

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Bibliographische Detailangaben
Hauptverfasser: Haidong Guo, Rector, D.M., la Rue, G.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog integrated circuits
Analog-digital conversion
Calibration
CMOS technology
Integrated circuit noise
Interleaved codes
MIM capacitors
Power dissipation
Sensor arrays
Voltage
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Beschreibung
Zusammenfassung:A 6.2 mW 16-bit 500 kSps charge redistribution self calibrating successive approximation analog-to-digital converter (ADC) is described. It has an input range of 2 V, a resolution of 16 bits and operates with +/- 1.5 V supplies. Simulations show a signal-to-noise ratio of 95 dB for an effective accuracy of 15 bits in 0.25 mum CMOS technology. A novel interleaving architecture and an improved comparator design contribute to reducing the power while maintaining the accuracy and speed. The ADC is intended to digitize the amplified neurophysiological signals from a companion 16-channel sensor IC
ISSN:1947-3834
1947-3842
DOI:10.1109/WMED.2005.1431628