Functional verification based on the EFSM model

Functional verification based on the EFSM model

The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults.

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Bibliographische Detailangaben
Hauptverfasser: Fummi, F., Marconcini, C., Pravadelli, G.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Automata
Automatic test pattern generation
Circuit faults
Circuit testing
Electrical fault detection
Fault detection
Hardware design languages
Observability
Sequential circuits
Test pattern generators
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Beschreibung
Zusammenfassung:The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults.
ISSN:1552-6674
2471-7827
DOI:10.1109/HLDVT.2004.1431240